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Title : ISSCC 2021: Samsung 0.64um Pixel
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ISSCC 2021: Samsung 0.64um Pixel

This year, ISSCC has not released its usual media kit with preview snippets of the most interesting papers. So, I'm filling the void with few such snippets. The first one is about Samsung 0.64um pixel:

"1/2.74-inch 32Mpixel-Prototype CMOS Image Sensor with 0.64μm Unit Pixels Separated by Full-Depth Deep-Trench Isolation"

by JongEun Park, Sungbong Park, Kwansik Cho, Taehun Lee, Changkyu Lee, DongHyun Kim, Beomsuk Lee, SungIn Kim, Ho-Chul Ji, DongMo Im, Haeyong Park, Jinyoung Kim, JungHo Cha, Taehoon Kim, In-Sung Joe, Soojin Hong, Chongkwang Chang, Jingyun Kim, WooGwan Shim, Taehee Kim, Jamie Lee, Donghyuk Park, EuiYeol Kim, Howoo Park, Jaekyu Lee, Yitae Kim, JungChak Ahn, YoungKi Hong, ChungSam Jun, HyunChul Kim, Chang-Rok Moon, Ho-Kyu Kang

"...a 0.7μm pixel sensor was demonstrated with acceptable photodiode (PD) full-well capacity (FWC) of >6,000e as well as signal-to-noise ratio (SNR) of ~32dB without optical/electrical crosstalk by employing state-of-the-art full-depth deep-trench isolations (FDTIs). However, further scaling requires elaborate fabrication innovation and layout ideas. At the same time, meeting every aspect of pixel performance compared to the previous generation becomes even more difficult, e.g., with respect to dark or illuminated characteristics, fixed-pattern or temporal noises, etc. The latter, in particular, is associated with in-pixel source-follower (SF) amplifiers. Therefore, electrical performance of scaled in-pixel transistors cannot be overlooked. In this paper, a 32-megpixel (MP) CIS with 0.64μm unit pixels is demonstrated with FDTI design. Innovations in terms of fabrication and design to achieve this performance with scaling are discussed."

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