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Title : TSMC Publishes Noise Data for Pixel-Level Stacked Circuits
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TSMC Publishes Noise Data for Pixel-Level Stacked Circuits

TSMC publishes an IEEE Journal on Electron Device Society paper "Statistical Analysis of Random Telegraph Noises of MOSFET Subthreshold Currents Using a 1M Array Test Chip in a 40 nm Process" by Calvin Yi-Ping Chao; Meng-Hsu Wu; Shang-Fu Yeh; Chin-Hao Chang; Chi-Lin Lee; Chin Yin; Kuo-Yu Chou; Honyih Tu that has an interesting noise data for pixel-stacked circuits that operate at pA currents per pixel:

"It is difficult to measure the random telegraph noises (RTN) of MOSFET subthreshold currents at the sub-pA level directly and accurately. In this work, we used a charge integration method similar to the operation of the CMOS image sensors (CIS) to characterize the RTN of subthreshold currents approximately from 1 fA to 1 nA, using a test chip of 1M cell array in a 40 nm process. We found that each RTN trap was active only within a specific window of gate voltages. The trap became less active or inactive outside the corresponding window of operations. We showed that the sets of RTN-active devices under different gate voltages were different. Furthermore, the choice of sampling frequency in measuring RTN and the number of sampled data points determined the observable range of RTN emission and capture time constants. For the data measured by sampling periods of 3.82 s, 299 ms, and 372 μs , different sets of RTN traps were observed with different spans of time constants. The combined time constants range was about 7 orders of magnitude. For single-trap RTN, we found and verified a relation between the probability of trap occupancy (PTO) and the ratio of root-mean-square random noise (RN) versus the RTN amplitude."

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