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Title : PhD Thesis on Dynamic Range Improvements
link : PhD Thesis on Dynamic Range Improvements

PhD Thesis on Dynamic Range Improvements

A PhD thesis titled "Proposal of Architecture and Circuits for Dynamic Range Enhancement of Vision Systems on Chip designed in Deep Submicron Technologies" by from Universidad de Sevilla is now available to the public. The thesis is by Sonia Vargas Sierra who did this work at the Image Sensor group of Microelectronic Institute of Seville.

Although the thesis is from a few years ago, some of the content in the thesis may be of interest now due to recent developments in vertical integrated technologies.

From the Preface:

The work presented in this thesis proposes new techniques for dynamic range expansion in electronic image sensors. Since Dynamic Range (DR) is defined as the ratio between the maximum and the minimum measurable illuminations, the options for improvement seem obvious; first, to reduce the minimum measurable signal by diminishing the noise floor of the sensor, and second, to increase the maximum measurable light by increasing the sensor saturation limit.

In our case, we focus our studies to the possibility of providing DR enhancement functionality in a single chip, without requiring any external software/hardware support, composing what is called a Vision-System-on-Chip (VSoC). In order to do so, this thesis covers two approaches. Chronologically, our first option to improve the DR relied on reducing the noise by using a fabrication technology that is specially devoted to image sensor fabrication, a so-called CMOS Image Sensor (CIS) technology. However, measurements from a test chip indicated that the dynamic range improvement was not sufficient to our purposes (beyond the 100dB limit). Additionally, the technology had some important limitations on what kind of circuitry can be placed next to the photosensor in order to improve its performance. Our second approach has consisted in, first, designing a tone mapping algorithm for DR expansion whose computational needs can be easily mapped onto simple signal conditioning and processing circuitry around the photosensor, and second, designing a test chip implementing this algorithm in a standard CMOS technology.

This thesis is organized in five chapters. Chapter 1 describes the main concepts involved in image sensors focusing in High Dynamic Range (HDR) operation. Chapter 2 presents the study of an image sensor optimized technology in order to be considered for dynamic range improvement techniques. Chapter 3 describes an innovative tone mapping algorithm used to optimize the compression of HDR scenes. Chapter 4 introduces the image sensor chip that has been designed and fabricated, which implements the new tone mapping algorithm. Chapter 5 shows the experimental results and evaluation of the performance of the chip. 

Link to download thesis pdf: https://idus.us.es/handle/11441/130619

A couple of references related to the topic of this thesis: 

1. S. Vargas-Sierra et al., "A 151 dB high dynamic range CMOS image sensor chip architecture with tone mapping compression embedded in-pixel", IEEE Sensors J. Jan. 2015. https://ieeexplore.ieee.org/document/6860247 
2. Mori et al., "A 4.0 μm Stacked Digital Pixel Sensor Operating in a Dual Quantization Mode for High Dynamic Range," IEEE TED June 2022 issue. https://ieeexplore.ieee.org/abstract/document/9762367/

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