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Title : Review paper on stacking and interconnects for CMOS image sensors
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Review paper on stacking and interconnects for CMOS image sensors

In an ASME J. Electron. Packag. paper titled "Advancement of Chip Stacking Architectures and Interconnect Technologies for Image Sensors" Mei-Chien Lu writes:

Numerous technology breakthroughs have been made in image sensor development in the past two decades. Image sensors have evolved into a technology platform to support many applications. Their successful implementation in mobile devices has accelerated market demand and established a business platform to propel continuous innovation and performance improvement extending to surveillance, medical, and automotive industries. This overview briefs the general camera module and the crucial technology elements of chip stacking architectures and advanced interconnect technologies. This study will also examine the role of pixel electronics in determining the chip stacking architecture and interconnect technology of choice. It is conducted by examining a few examples of CMOS image sensors (CIS) for different functions such as visible light detection, single photon avalanche photodiode (SPAD) for low light detection, rolling shutter, and global shutter, and depth sensing and light detection and ranging (LiDAR). Performance attributes of different architectures of chip stacking are overviewed. Direct bonding followed by Via-last through silicon via (Via-last TSV) and hybrid bonding (HB) technologies are identified as newer and favorable chip-to-chip interconnect technologies for image sensor chip stacking. The state-of-the-art ultrahigh-density interconnect manufacturability is also highlighted.

Schematics of an imaging pixel array, circuit blocks and a typical 4 T-APS pixel electronics

Exemplary schematics of front side illuminated sensors (FSI-CIS) and back side illuminated sensors (BSI-CIS)

Schematics of ceramic leadless chip carrier ceramic image sensor package at the top and imaging ball grid array image sensor package at the bottom

Schematics of two camera modules with image sensor packages at the bottom parts under lens modules

A micrograph of the partitioned top and bottom circuit blocks of the first stacked image sensor from SONY

Schematics of Stacked BSI pixel chip to circuit chip bonded at dielectric surfaces with peripheral via-last TSVs

Dual-photodiode stacked chips BSI-CIS processed by 65 nm/14 nm technologies

Chip-to-chip bonding and interconnect methods with (a) direct dielectric bonding followed by via-last TSVs for chip-to-chip interconnect, (b) hybrid bonding at peripheral area, and (c) hybrid bonding under pixel arrays

Pixel array, DRAM, and logic three-chip stacked image sensor by Sony Corp using dielectric-to-dielectric bonding followed by via-last TSV interconnects at peripheral areas

A SONY stacked-chip GS using pixel-level integration with (a) the pixel array chip, (b) the processor chip, and (c) cross section of stacked chips using hybrid bonding interconnects

Schematics of pixel electronics partition and cross section view of OmniVision stacked-chip pixel level connections

A schematic of pixel electronics for ToF SPAD image sensor

A cross section of a NIR SPAD ToF image sensor using hybrid bonding at chip-to-chip interface.

Schematic of a 3D stacked SPAD image sensor: (a) cross section view of pixel array chip stacked on CMOS circuitry chip by hybrid bonding and (b) diagram of pixel electronics

A chip floor plan and pixel array for a two-tier IR SPAD sensor for LiDAR application [14]

Short wavelength infrared sensor using InP/InGaAs/InP photodiodes bond to readout circuitry in silicon chip by pixel-level integration: (a) flip-chip bumps and (b) Cu-Cu hybrid bonds

Process flow of via-last TSV for chip-to-chip interconnect

Process flow of Direct Bond Interconnect

Link to full paper (open access): https://asmedigitalcollection.asme.org/electronicpackaging/article/144/2/020801/1115637/Advancement-of-Chip-Stacking-Architectures-and

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